The CXL Consortium announced the release of the CXL 3.0 specification to add new levels of flexibility and composability to current and future data centers. CXL 3.0, based on the previous technology, offers a range of advanced features and benefits, including doubling the bandwidth with the same latency. It is backward compatible with the CXL 2.0, CXL 1.1 and CXL 1.0 specifications.
Computer Express Link (CXL) is an industry-standard open interconnect providing memory coherency and semantics using high-bandwidth, low-latency connectivity between the host processor and peripherals such as accelerators, buffers, and I/O interfaces. Its latest version, CXL 3.0, adds advanced switching and fabric capabilities, efficient peer-to-peer communications, and granular resource sharing across multiple compute domains.
Siamak Tavallaei, president of the CXL consortium, said CXL technology is rapidly evolving to meet the demands of data centers. “Modern data centers require heterogeneous and composable architectures to support compute-intensive workloads for applications such as artificial intelligence and machine learning,” he added. “The CXL 3.0 specification will enable new usage patterns in a composable disaggregated infrastructure.”
Kevin Krewell, principal analyst at TIRIAS Research, agrees that the CXL consortium has made exceptionally rapid progress in delivering this critical specification to the industry. “CXL 3.0 is a significant step forward in enabling heterogeneous computing.”
Travis Karr, General Manager of Interconnect SoCs at Rambus, agrees on the transformative potential of CSL technology and its latest release. “The introduction of CXL 3.0 meets the needs of next-generation data centers with 64 GT/s signaling and a new level of scalability.”
The CXL Consortium will showcase the new features of CXL 3.0 at the Flash Memory Summit (FMS) taking place August 2-4 at the Santa Clara Convention Center.